1. Field of the Invention
This invention relates to the field of circuitry for processing digital signals. More particularly, this invention relates to dynamic circuitry having state signal which is reset to a predetermined value and then selectively changed from that predetermined value in dependence upon an input signal value.
2. Description of the Prior Art
A known problem within circuitry for processing digital signals is metastability. Metastability can arise when a signal value is sampled at a time close to when that signal value undergoes a transition. For example, a buffer circuit as illustrated in FIG. 1 of the accompanying drawings may serve as a synchroniser between clock domains and uses conventional flip-flops rather than dynamic circuits (buffers). The circuitry of FIG. 1 is configured to sample an input signal DCK1 from clock domain CK1 upon the rising edge of a different clock signal CK2. As illustrated in FIG. 1, if the input signal DCK1 undergoes a transition close to the rising edge of the clock signal CK2, then the output of the first flip-flop DFF1 can become metastable and adopt an intermediate signal value rather than clearly adopting either the high voltage state or the low voltage state. The metastability of the signal Q1 output from the first flip-flop DFF1, may then go on to produce metastability in the output of the second flip-flop DFF2 as illustrated. Such metastability problems become more of a concern when the design of a circuit is such that the proper value for the input signal DCK1 will not settle until shortly before the time at which it will be sampled. Indeed, in order to increase the performance of some circuits, it is known to increase the clock frequency to reach a limiting condition in which input signals to be sampled settle to their true values just before the time at which they are sampled. While this approach may increase the performance of the circuitry, it also increases the probability of errors occurring due to metastability as illustrated in FIG. 1.